Wallace Tree 4-bit Multiplier

Details:
Digital Integrated Circuits course (ESE570), April 2011 - May 201

Collaboration:
Eric Chen (EE '12) and Varun Sampath (CMPE '12).

Description:
Implemented a 4-bit signed Wallace Tree multiplier in 0.6µm CMOS.
Designed, laid out, simulated, and verified various components to the 4-bit multiplier in Cadence.
Circuit was built modularly with each component being tested and verified before going on to the next step.

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